1. Field of the Invention
The present invention relates to a bank control circuit in a Rambus DRAM capable of reducing circuit area by disposing one control circuit and one address latch circuit in every two banks.
2. Description of the Related Art
FIG. 1 is a block diagram of a conventional Rambus DRAM comprising: memory blocks 10 including an upper and a lower memory block units 12, 14 comprising 16 memory banks respectively; an upper and a lower series/parallel shifter units 16, 18 for performing series/parallel conversion to interface write and read data of the memory bank with outside; an input/output terminal 20 for outputting read data received through the upper and lower series/parallel shifter units 16, 18 to outside and for outputting write data received from outside to the upper and lower series/parallel shifter units 16, 18; and a control unit 22 for controlling operations of the upper and lower series/parallel shifter units 16, 18.
The memory blocks 10 have 32 memory banks, including the upper memory block unit 12 and the lower memory block unit 14 comprising 16 banks respectively.
The upper series/parallel shifter unit 16 converts 128 bit parallel data RDA_top[127:0] read in the upper memory block unit 12 to 16 bit data EvenRDA_top[7:0], OddRDA_top[7:0] and outputs the result and the lower series/parallel shifter unit 18 converts 128 bit parallel data RDA_bot[127:0] read in the lower memory block unit 14 to 16 bit data Even RDA_bot [7:0], OddRDA_bot [7:0] and outputs the result.
The upper and lower series/parallel shifter units 16, 18 generally perform two operations. One of them is series-parallel conversion for converting 8 bit series data input 8 times in write operation to 128 bit and the other is parallel-series conversion for converting 128 bit data read from memory block in read operation to 8 bitxc3x978.
In a write operation, two upper and lower series/parallel shifter units 16, 18 simultaneously transmit inputted write data to the upper memory block unit 12 and the lower memory block unit 14 respectively and only the data selected by write address are recorded in the memory block 10. And, in read operation, two upper and lower series/parallel shifter units 16, 18 receive read data through each memory block 10 and transmit them to output terminal.
FIG. 2 is a block diagram of conventional memory bank control circuit disposed in the upper memory block 12 (or in the lower memory block 14) shown in FIG. 1. As illustrated, the conventional memory bank control circuit comprises: 16 memory bank units 30 less than 0 greater than xcx9c30 less than 15 greater than  for storing data; 17 sense amp units 40 less than 0 greater than xcx9c40 less than 16 greater than  disposed on upper parts and lower parts of each memory bank for sensing data in write and read operations; 17 sense amp driver units 50 less than 0 greater than xcx9c50 less than 16 greater than  for respectively controlling operations of the sense amp units 40 less than 0 greater than xcx9c40 less than 16 greater than ; xe2x89xa0main word line and sub word line driver units 60 less than 0 greater than xcx9c60 less than 15 greater than  for driving word lines and sub word lines of the memory bank units 30 less than 0 greater than xcx9c30 less than 15 greater than ; and 16 control units and address latch units 70 less than 0 greater than xcx9c70 less than 15 greater than  for receiving active signals, precharge signals and global address signals from outside and generating sense amp control signals corresponding to address signals to control sense amp driver unit, main word line and sub word line driver unit and bit lines in memory bank, main word line control signals, sub word line control signals and bit line equalizing signals.
One control unit and one address latch unit are disposed in every memory bank unit 30 less than 0 greater than xcx9c30 less than 15 greater than . When the active signal and the precharge signal are generated as global signals, the control unit and the address latch unit 70 less than 0 greater than xcx9c70 less than 15 greater than  of each memory bank check whether or not the received global address signals are address signals of its memory bank and then if the bank addresses correspond to each other, the memory banks are controlled to operate in active mode or precharge mode. That is, the control unit corresponding to the bank address and the address latch unit operate main word line and sub word line driver units of the relevant memory bank and 2 sense amp driver units on the upper and the lower parts of the relevant memory bank. Here, the control unit and the address latch unit selected by the bank address maintain word lines in the memory bank although external global address signals are changed by latching addresses received in active mode.
When nth memory bank 30 less than n greater than  is selected by the global address signal, all of (nxe2x88x921)th, nth and (n+1)th memory banks 30 less than nxe2x88x921 greater than , 30 less than n greater than , 30 less than n+1 greater than  are precharged and then the nth memory bank 30 less than n greater than  is activated. For example, if memory bank 130 less than 1 greater than  is selected, then memory bank 030 less than 0 greater than , memory bank 130 less than 1 greater than  and memory bank 230 less than 2 greater than  are all precharged and then memory bank 130 less than 1 greater than is activated. And, when the memory bank 130 less than 1 greater than  is activated, the memory bank 030 less than 0 greater than  and the memory bank 230 less than 2 greater than  are not activated until the memory bank 130 less than 1 greater than  is precharged.
However, the conventional bank control unit of Rambus DRAM has several drawbacks. For example, there is a problem of increased layout area since each memory bank has control units and address latch units.
Therefore, the present invention has been made to solve the problems of the conventional bank control unit of Rambus DRAM. One object of this invention is to provide a bank control circuit capable of reducing circuit area by disposing one control circuit and one address latch circuit in every two banks.
According to the present invention, the semiconductor memory device wherein a dependent bank operation is performed, comprises: a plurality of banks including memory cells; a plurality of address latch circuits, shared by two adjacent banks respectively, for receiving global address signals and latching local address signals of the selected bank; and a plurality of control circuits, shared by two adjacent banks respectively, for generating control signals and determining the specific bank that is to be activated.
As described above, according to the present invention, one control circuit and address latch circuit is shared by two banks, thereby reducing circuit area.
The above objects and other features and advantages of the present invention will become more apparent after reading the following detailed description when taken in conjunction with the drawings.